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16-BIT TRI-PORT BUS EXCHANGER
Integrated Device Technology, Inc.
IDT73720/A
FEATURES:
* High-speed 16-bit bus exchange for interbus communication in the following environments: -- Multi-way interleaving memory -- Multiplexed address and data busses * Direct interface to R3051 family RISChipSetTM -- R3051TM family of integrated RISControllerTM CPUs -- R3721 DRAM controller * Data path for read and write operations * Low noise 12mA TTL level outputs * Bidirectional 3-bus architecture: X, Y, Z -- One CPU bus: X -- Two (interleaved or banked) memory busses:Y & Z -- Each bus can be independently latched * Byte control on all three busses * Source terminated outputs for low noise and undershoot control * 68-pin PLCC and 80-pin PQFP package * High-performance CMOS technology.
DESCRIPTION:
The IDT73720/A Bus Exchanger is a high speed 16-bit bus exchange device intended for inter-bus communication in interleaved memory systems and high performance multiplexed address and data busses. The Bus Exchanger is responsible for interfacing between the CPU A/D bus (CPU address/data bus) and multiple memory data busses. The 73720/A uses a three bus architecture (X, Y, Z), with control signals suitable for simple transfer between the CPU bus (X) and either memory bus (Y or Z). The Bus Exchanger features independent read and write latches for each memory bus, thus supporting a variety of memory strategies. All three ports support byte enable to independently enable upper and lower bytes.
FUNCTIONAL BLOCK DIAGRAM
OEYL 8 LEXY Y-WRITE LATCH 16 8 8 LEYX 8 8 OEXL X0:7 X8:15 OEXU 8 8 M U 16 X OEXU OEXL OEYU OEYL OEZU OEZL 16 Z-READ LATCH 16 8 Z-WRITE LATCH 16 8 OEZU
NOTE: 1. Logic equations for bus control: OEXU = T/R* . OEU*; OEXL = T/R* . OEL*; OEYU = T/R . PATH . OEU* OEYL = T/R . PATH . OEL*; OEZU = T/R . PATH* . OEU*; OEZL = T/R . PATH* . Figure 1. 73720 Block Diagram
Y0:7 Y8:15 8 (Even Path)
16
Y-READ LATCH
OEYU 16
PATH BUS CONTROL T/R OEU OEL
8
8 LEZX
OEZL 8 8 Z0:7 Z8:15 (Odd Path)
2527 drw 01
16 LEXZ
OEL*
RISChipSet, RISController, R305x, R3051, R3052 are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1995 Integrated Device Technology, Inc.
AUGUST 1995
11.5
DSC-2046/6
1
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
X7 X6 X5 X4 X3 X2 X1 X0 GND VCC Z15 Z14 Z13 Z12 Z11 Z10 GND
9 8 7 6 5 4 3 2
GND X8 X9 X10 X11 X12 X13 X14 X15 GND VCC PATH OEU LEYX LEZX Y0 Y1
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
Pin 1 Designator
J68-1
52 51 50 49 48 47 46 45
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 GND VCC LEXZ OEL LEXY T/R GND
GND X7 X6 X5 X4 X3 X2 X1 X0 GND VCC Z15 Z14 Z13 Z12 Z11 Z10
GND NC NC X8 X9 X10 X11 X12 X13 X14 X15 GND VCC PATH OEU LEYX LEZX Y0 Y1 GND
1 2 3 4 5 6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60
NC NC GND
59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43
GND Y2 Y3 Y4 Y5 Y6 Y7 Y8 GND VCC Y9 Y10 Y11 Y12 Y13 Y14 Y15
2527 drw 02
PLCC TOP VIEW
Pin 1 Designator
7 8 9 10 11 12 13 14 15 16 17 18
PQ80-1
19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 GND VCC LEXZ OEL LEXY T/R NC NC GND
Y2 Y3 Y4 Y5 Y6 Y7 Y8 GND VCC Y9 Y10 Y11 Y12 Y13 Y14 Y15 NC GND
GND NC
PQFP TOP VIEW
2527 drw 03
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IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal X(0:15) Y(0:15) Z(0:15) LEXY LEXZ LEYX LEZX PATH T/R I/O I/O I/O I/O I I I I I I I I Description Bidirectional Data Port X. Usually connected to the CPU's A/D (Address/Data) bus. Bidirectional Data port Y. Connected to the even path or even bank of memory. Bidirectional Data port Z. Connected to the odd path or odd bank of memory. Latch Enable input for Y-Write Latch. The Y-Write Latch is open when LEXY is HIGH. Data from the X-port (CPU) is latched on the HIGH-to-LOW transition of LEXY Latch Enable input for Z-Write Latch. The Z-Write Latch is open when LEXZ is HIGH. Data from the X-port (CPU) is latched on the HIGH-to-LOW transition of LEXZ. Latch Enable input for the Y-Read Latch. The Y-Read Latch is open when LEYX is HIGH. Data from the even path Y is latched on the HIGH-to-LOW transition of LEYX. Latch Enable input for the Z-Read Latch. The Z-Read Latch is open when LEZX is HIGH. Data from the odd path Z is latched on the HIGH-to-LOW transition of LEZX Even/Odd Path Selection. When high, PATH enables data transfer between the X-Port and the Y-port (even path). When LOW, PATH enables data transfer between the X-Port and the Z-Port (odd path). Transmit/Receive Data. When high, Port X is an input Port and either Port Y or Z is an output Port. When LOW, Port X is an output Port while Ports Y & Z are input Ports Output Enable for Upper byte. When LOW, the Upper byte of data is transfered to the port specified by PATH in the direction specified by T/R . Output Enable for Lower byte. When LOW, the Lower byte of data is transfered to the port specified by PATH in the direction specified by T/R .
2527 tbl 02
OEU OEL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. -0.5 to +7.0 Mil. -0.5 to +7.0 Unit V
CAPACITANCE (TA = +25C, F = 1.0MHZ)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 12 Unit pF pF
TA TBIAS TSTG PT IOUT
0 to +70 -55 to +125 -55 to +125 1.0 50
-55 to +125 -65 to +135 -65 to +125 1.0 50
C C C W mA
NOTE: 2527 tbl 04 1. This parameter is guaranteed by device characterization, but is not production tested.
TRUTH TABLE
Path L L H H X X X T/R R L H L H X X X
OEU
L L L L H H L
OEL
L L L L H L H
Functionality ZX (16-bits)-Read Z(1) XZ (16 bits)-Write Z(1) YX (16-bits)-Read Y(2) XY (16 bits)-Write Y(2) All output buffers are disabled Transfer of lower 8 bits (0:7) as per PATH & T/R Transfer of upper 8 bits (8:15) as per PATH & T/R
NOTE: 2527 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTES: 2527 tbl 01 1. For ZX and XZ transfers, Y-port output buffers are tristated. 2. For YX and XY transfers, Z-port output buffers are tristated.
11.5
3
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
ARCHITECTURE OVERVIEW
The Bus Exchanger is used to service both read and write operations between the CPU and the dual memory busses. It includes independent data path elements for reads from and writes to each of the memory banks (Y and Z). Data flow control is managed by a simple set of control signals, analogous to a simple transceiver. In short, the Bus Exchanger allows bidirectional communication between ports X and Y and ports X and Z as illustrated in figure 1. The data path elements for each port include: Read Latch: Each of the memory ports Y and Z contains a transparent latch to capture the contents of the memory bus. Each latch features an independent latch enable. Write Latch: Each memory port Y and Z contains an independent latch to capture data from the CPU bus during writes. Each memory port write latch features an independent latch enable, allowing write data to be directed to a specific memory port without disrupting the other memory port. Data Flow Control Signals T/R (Transmit/Receive). This signal controls the direction R of data transfer. A transmit is used for CPU writes, and a receive is used for read operations. OEU OEL are the output enable control signals to select OEU, upper or lower bytes of all three ports. Path: The path control signal is used to select between the even memory path Y and the odd memory path Z during read or write operations. Path selects the memory port to be connected to the CPU bus (X-port), and is independent of the latch enable signals. Thus, it is possible to transfer data from one memory port to the CPU bus (X) while capturing data from the other memory port.
element onto the CPU bus, while the first bank is presented with a new data element. Transparent Mode The Bus Exchanger may be used as a data transceiver by leaving all latches open or transparent. Memory Write Operations Memory write operations also consist of two distinct stages. During one stage, the write data is captured into the selected memory port write latch. During a later stage, the memory is presented on the memory port bus The write operation is selected by driving T/R HIGH. Writes are thus performed using the Path input to select the memory port (Y or Z). The LEXY/LEXZ capture data in the corresponding Write Latch. Note that it is possible to utilize the bus exchanger's write resources as an additional write buffer, if desired; the CPU A/D bus can be freed up once the data has been captured by the Bus Exchanger.
APPLICATIONS
Use as Part of the R3051 Family ChipSet Figure 2 shows the use of the Bus Exchanger in a typical R3051 based system. In write transactions, the R3051 drives data on the CPU bus. The latch enables are held open through the entire write; thus, the bus exchanger is used like a transceiver. The appropriate LEXY/LEXZ signal is derived from ALE (Logic LOW- indicating that the processor is driving data) and the low order address bit. The rising edge of Wr from the CPU, ends the write operation. During read transactions, the memory system is responsible for generating the input control signals to cause data to be captured at the memory ports. The memory controller is also responsible for acknowledging back to the CPU that the data is available, and causing the appropriate path to be selected. The R3721 DRAM controller for the R3051 family uses the transparent latches of the read ports. The R3721 directly controls the inputs of the bus exchanger, during both reads and writes. Consult the R3721 data sheet for more information on these control signals. Use in a general 32-bit System Figures 3 and 4 illustrate the use of the Bus Exchanger in a 32-bit microprocessor based system. Note the reduced pin count achieved with the Bus Exchanger.
MEMORY READ OPERATIONS
Latch Mode In this mode the read operation consists of two stages. During the first stage, the data present at the memory port is captured by the read latch for that memory port. During a subsequent stage, data is brought from a selected memory port to the CPU A/D port X by using output enable control. The read operation is selected by driving T/R LOW. The read is managed using the Path input to select the memory port (Y or Z); the LEYX/LEZX enable the data capture into the corresponding Read Latch. In this way, memory interleaving can be performed. While data from one bank is output onto the CPU bus, data on the other bank is captured in the other memory port. In the next cycle, the Path input is changed, enabling the next data
11.5
4
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
Clk2xIn
IDT R3051 FAMILY RISController ADDRESS/DATA R305x LOCAL BUS CONTROL
IDT79R3721 DRAM CONTROLLER
DRAM
DRAM
IDT73720 BUS EXCHANGER (2)
Figure 2. Bus Exchanger Used in R3051 Family System
2527 drw 04
CPU 32 4 x (74FCT373) 2 x (73720)
CPU 32 4 x (74FCT373) 2 x (73720)
DRAM 1 Address Data Bus Chip Count = 2 Pin Count = 136
DRAM 2
DRAM 1 Address Data Bus Chip Count = 2 Pin Count = 136
DRAM 2
CPU
32
CPU
32
4 x (74FCT373)
4 x (74FCT245)
4 x (74FCT245)
4 x (74FCT373)
4 x (74FCT543)
4 x (74FCT543)
DRAM 1 Address Data Bus Chip Count = 8 Pin Count = 160
DRAM 2
DRAM 1 Address Data Bus Chip Count = 8 Pin Count = 192
DRAM 2
2527 drw 05
2527 drw 06
Figure 3. CPU System with Transparent Data Path (2-way Interleaving) 11.5
Figure 4. CPU System with Latched Data Path (2-way Interleaving) 5
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 5%, TA = 0C to +70C)
Symbol VIH VIL IIH IIL VIK IOS(3) VOH VOL VH ICC ICC ICCD Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Clamp Diode Voltage Short Circuit Current Output HIGH Voltage Output LOW Voltage Input Hysteresis All inputs Quiescent Power Supply Current Quiescent Power Supply Current Dynamic Power Supply Current(5) Test Conditions(1) Min. 2.0 -- -- -- -- -- -- -60 2.4 -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -0.7 -- 3.3 0.3 200 0.2 0.5 0.25 Max. -- 0.8 5.0 5.0 -5.0 -5.0 -1.2 -200 -- 0.5 -- 1.5 2.0 0.5 Unit V V A A V mA V V mV mA mA/ Input mA/ MHz
VCC = Max., VIH = 2.7V VCC = Max., VIL = 0.5V
Inputs only I/O pins Inputs only I/O pins
VCC = Min., IIN = -18mA VCC = Max., VO = GND VCC = Min., VIN = VIH or VIL, IOH = -12mA VCC = Min., VIN = VIH or VIL, IOL = 12mA VCC = 5V VCC = Max. VIN = GND or VCC VCC = Max. VIN =3.4 V(4) VCC = Max. VIN = VCC or GND Outputs Disabled OE = VCC One Input Toggling 50 % Duty Cycle VCC = Max. VIN = VCC or GND Outputs Disabled 50 % Duty Cycle OE = VCC fi = 10MHz One Bit Toggling
IC
Total Power Supply Current(6)
--
2.7
6.5
mA
NOTES: 1. For conditions shown as max. or min., use appropriate VCC value. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second. 4. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 5. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megaherz.
2527 tbl 05
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure 5
2527 tbl 06
11.5
6
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 5%, TA = 0 to +70C)
73720A Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tHZ tLZ tZH tZL tHZ tLZ tZH tZL tSU tH tW Parameter X to Y & X to Z Latches enabled Y to X & Z to X Latches enabled Latch Enable to Y & Z Port Latch Enable to X Path to X Port Propagation Delay Y & Z Port Disable Time (T/R, PATH, OEU, OEL)(3) Y & Z Port Enable Time (T/R, PATH, OEU, OEL)(3) X-Port DisableTime (T/R, OEU, OEL)(3) X-Port Enable Time (T/R, OEU, OEL)(3) Port to LE Set-up time Port to LE Hold time LE Pulse Width, HIGH or LOW
(2)
73720 Min.(2) 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 1.5 4 Max. 7.5 7.5 8.5 8.5 8.5 9.5 10.5 9.5 10.5 -- -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns
2527 tbl 07
Test Conditions(1) CL = 50pF RL = 500 Ohms
Min.(2) 2.0 2.0
Max. 6.0 6.0 7.0 7.0 7.0 8.5 9.5 8.5 9.5 -- -- --
LEXY to Y LEXZ to Z LEYX to X LEZX to X
2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 1.5 3
NOTES: 1. All timings are referenced to 1.5 V. 2. Minimum Delay Times, Enable Times, Disable Times and Pulse Width are guaranteed by design, but not tested. 3. Bus turnaround times are guaranteed by design, but not tested. (T/R enable/disable times).
TEST CIRCUITS AND WAVEFORMS
VCC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500
2527 drw 07
SWITCH POSITION
7.0V
Test Disable LOW Enable LOW All Other Tests Open
DEFINITIONS: 2527 tbl 08 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Switch Closed
V OUT
Figure 5. Test Circuit for all outputs
11.5
7
IDT73720/A 16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
SET-UP, HOLD AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL tSU 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
2527 drw 08
PULSE WIDTH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE 1.5V
tSU
tH
1.5V
tREM
2527 drw 09
tH
PROPAGATION DELAY
3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
2527 drw 10
ENABLE AND DISABLE TIMES
ENABLE DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V
2527 drw 11
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPLH tPLH
CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH LOW CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH tPLZ 3.5V 1.5V
VOL
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control DisableHIGH. 2. Pulse Generator for All Pulses: Rate 1.0 MHz; ZO 50; tF 2.5ns; tR 2.5ns.
ORDERING INFORMATION
IDT XXXXX Device Type X Speed X Package X Process/ Temperature Range Blank J PQF Blank A 73720 Commercial Temperature Range 68-Pin PLCC 80-Pin PQFP Standard Speed High Speed Bus Exchanger
2527 drw 12
11.5
8

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